This Invention relates to electro-static-discharge (ESD) protection devices, and more particularly to ESD protection using a common-discharge line (CDL).
Mixed-signal integrated circuit (IC) chips often have multiple power and ground supply pins and internal busses. Basic ESD-protection devices and structures are normally placed on each input/output pin and provide protection for an ESD zap between the pin and one of the power/ground buses. Protection for zaps between the pin and the other ground and power buses is minimal. Pin-to-pin ESD protection can also be inadequate.
More recently, ESD protection structures or shorting devices have been added between each possible pair of the multiple power and ground buses. These devices extend ESD protection regardless to which ground or power supply the local pin""s ESD structure is attached to.
Another advance is an additional internal bus used for ESD protection. This internal bus is known as a common discharge line (CDL) and is not one of the power or ground buses. The CDL provides a low-impedance and symmetric path for ESD currents even when ESD pulses are applied across two I/O pins. However, buffer circuits in the core, such as large inverters with large widths and minimum layout rules between a power bus and a ground bus can be easily triggered on during a VCC-to-VSS zapping configuration, resulting in them carrying too much of the ESD current and being damaged.
Another problem with CDL schemes using grounded-gate NMOS protection devices (with both source and body tied together) is that noise from I/O devices can be coupled through the CDL to core circuits. Local p-well or p-substrate taps near the grounded-gate ESD-protection devices can couple current to the CDL and then to core circuits.
What is desired is an ESD-protection scheme that has the versatility of a CDL structure, yet provides better protection for power-to-ground ESD events. A more noise-isolating CDL scheme is desired.